Staff Engineer (Heterogeneous III-V / Silicon Integration)

Staff Engineer (Heterogeneous III-V / Silicon Integration)

London

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

The Role

We are seeking highly skilled and motivated Staff Engineer to lead heterogeneous integration of III-V VCSEL arrays with silicon for our DX-1 accelerator. The role spans epitaxial design through to wafer/die-level integration with silicon substrates and driver ICs, taking large-format VCSEL arrays from process development into volume production. Covers device physics, integration process development, and system-level co-design, working closely with ASIC, electronics, packaging, and system architecture teams to ensure integrated arrays deliver the required bandwidth density, power efficiency, and yield.

Responsibilities

  • Drive integration strategy for III-V VCSEL arrays onto silicon (flip-chip, micro-transfer printing, wafer/die bonding, direct epitaxy)

  • End-to-end development of large-format VCSEL arrays from epi structure through to integrated, tested modules

  • Define and optimise epitaxial designs (quantum wells, DBRs, oxide/current confinement) with III-V/Si integration as a first-class constraintSpecify wafer growth, fab, and integration flows with external epi houses, III-V foundries, and silicon partners

  • Develop and qualify bonding, micro-transfer printing, alignment, and underfill processes at array scalePartner with modelling on thermal and thermo-mechanical analysis of integrated arrays

  • Characterise integrated devices: LIV, spectral, modulation bandwidth, array uniformity, thermal crosstalk, bonded-interface reliability

  • Solve scaling problems specific to large arrays — uniformity, yield, thermal management, mechanical stress, electrical fan-outWork with the ASIC team on interconnect parasitics across the III-V/Si interface

  • Interface with packaging and optics on coupling, tolerancing, and thermal pathing

  • Establish reliability methodologies (accelerated life test, bonded-interface qualification, FA)

  • Contribute to multi-generation roadmaps aligned with DX-1 scalingSupport transfer from R&D to pilot and volume manufacturing, including yield ramps and SPC

Skills & Experience

  • 7+ years in compound-semiconductor optoelectronics

  • Degree in Physics, EE, Materials Science, or related

  • Solid understanding of III-V materials systems (GaAs/AlGaAs, InP-based) and their Si integration constraints

  • Hands-on with one or more III-V/Si integration approaches: wafer bonding, micro-transfer printing, flip-chip on PIC, or direct epi of III-V on Si

  • Working knowledge of MBE/MOCVD and how epi design choices propagate into integration yield

  • Familiarity with high-speed modulation, bandwidth limitations, and electrical parasitics in heterogeneously integrated systems

  • Experience working with external foundries, epi suppliers, or integration partnersAble to interpret SEM, AFM, TEM, and bonded-interface characterisation data

  • Strong cross-functional collaboration — must be able to speak to silicon, packaging, and ASIC teams in their own language

Nice to have

  • Silicon photonic platforms and CMOS process flows

  • Reliability standards for datacom / compute-class optical interconnect (Telcordia, JEDEC)

  • Integrating lasers with custom driver ASICs at die or wafer level

  • Yield optimisation, SPC, and DoE for integrated optoelectronic processes

  • Thermal management and thermo-mechanical stress in dense laser arrays on dissimilar substrates

  • Python

Compensation & Equity

  • Competitive Salary, commensurate with your experience, skills, and location.

  • Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it.

  • Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer a £24k annual Living-Local Bonus if your residence is within 20 minutes of the office.

Health & Wellbeing

  • Premium Healthcare: Comprehensive BUPA medical and dental cover, including Medical History Disregarded (MHD), for complete peace of mind.

  • Time Off: 25 days of annual leave, plus all UK bank holidays.

The Workspace & Tech

  • Optimal Environment: High-spec noise-cancelling headphones and a fully ergonomic workstation designed for deep focus.

  • Rapid Prototyping: Access to our high-performance 3D printing lab for work, experimentation, and personal creative projects.

Life at the Office

  • Chef-prepared meals: if you need to work late.

  • Caffeine on Us: We’ve got you covered with a tab at our favourite local coffee shop.

Relocation & Global Mobility

  • Visa Sponsorship: We hire the best in the world. We offer full UK and international visa sponsorship.

  • Seamless Relocation: Whether you’re moving across the country or across the globe, our dedicated relocation partner provides funding and concierge support to get you settled.

We’re building fast and that includes our benefits. More exciting additions are coming soon for the OLIX crew.

If you are passionate about pushing the boundaries of what's possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join OLIX and be a key player in shaping the future of computing.

We do not accept unsolicited CVs from recruitment agencies, will not be liable for any fees, and prohibit unauthorised use of our company name in recruitment activities.

Staff Engineer (Heterogeneous III-V / Silicon Integration)

  • London: —

© 2026 – OLIX Computing

Elsewhere

© 2026 – OLIX Computing

Elsewhere

© 2026 – OLIX Computing

Elsewhere